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INTEGRATED CIRCUITS
DATA SHEET
TDA8354Q Full bridge current driven vertical deflection output circuit in LVDMOS
Preliminary specification File under Integrated Circuits, IC02 1998 Sep 03
Philips Semiconductors
Preliminary specification
Full bridge current driven vertical deflection output circuit in LVDMOS
FEATURES * Few external components * Highly efficient fully DC-coupled vertical output bridge circuit * Short rise and fall times of the vertical flyback switch * Guard circuit * Temperature (thermal) protection * High ElectroMagnetic Compatibility (EMC) because of common mode inputs * Guard signal in zoom mode. QUICK REFERENCE DATA SYMBOL DC supply VP Iq(av) Vflb IVflb(av) Io(p-p) Ii(diff)(p-p) Io(Vflb) Tstg Tamb Tj supply voltage average quiescent supply current flyback supply voltage average flyback supply current during scan during scan 7.5 - - - - t 1.5 ms - -55 -25 - 12 10 - - 500 - - - - PARAMETER CONDITIONS MIN. GENERAL DESCRIPTION
TDA8354Q
The TDA8354Q is a power circuit for use in 90 and 110 colour deflection systems for field frequencies of 25 to 200 Hz and 16 : 9 picture tubes. The circuit provides a DC-driven vertical deflection output circuit, operating as a highly efficient class G system. Due to the full bridge output circuit the deflection coils can be DC coupled. The IC is constructed in a low-voltage DMOS process that combines bipolar, CMOS and DMOS devices, to provide ruggedness.
TYP.
MAX.
UNIT
18 15 68 10
V mA V mA
2 x VP 45
Vertical circuit output current (peak-to-peak value) input current (peak-to-peak value) at pin 11 or 12 3.2 600 1.6 A A
Flyback switch peak output current A C C C
Thermal data (in accordance with IEC 747-1) storage temperature operating ambient temperature junction temperature +150 +75 150
ORDERING INFORMATION TYPE NUMBER TDA8354Q PACKAGE NAME DBS13P DESCRIPTION plastic DIL-bent-SIL power package; 13 leads (lead length 12 mm) VERSION SOT141-6
1998 Sep 03
2
Philips Semiconductors
Preliminary specification
Full bridge current driven vertical deflection output circuit in LVDMOS
BLOCK DIAGRAM
TDA8354Q
handbook, full pagewidth
Vo(guard) VP(B) 1 GUARD CIRCUIT 4
VP(A) 10
Vflb 7
Ii(diff) Ii(bias) Ii(diff)
Ii(pos)
12 9 COMPENSATION 13 CIRCUIT INPUT/ FEEDBACK 2 Vo(A) Ii(comp) Vi(M)
3
Vi(con)
Ii(diff) Ii(bias) Ii(diff)
Ii(neg)
11
5
Vo(B)
TDA8354Q
6 GNDB 8 GNDA
MGL461
Fig.1 Block diagram.
1998 Sep 03
3
Philips Semiconductors
Preliminary specification
Full bridge current driven vertical deflection output circuit in LVDMOS
PINNING SYMBOL Vo(guard) Vi(M) Vi(con) VP(B) Vo(B) GNDB Vflb GNDA Vo(A) VP(A) Ii(neg) Ii(pos) Ii(comp) PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 DESCRIPTION guard output voltage measuring resistor input conversion resistor input supply voltage B output voltage B ground B flyback supply voltage ground A output voltage A supply voltage A input power-stage (negative); includes Ii(bias) signal bias input power-stage (positive); includes Ii(bias) signal bias damping resistor compensation current input FUNCTIONAL DESCRIPTION
TDA8354Q
The vertical driver circuit is a bridge configuration. The deflection coil is connected between the output amplifiers, which are driven in phase opposition. The differential input circuit is current driven. The input circuit is special intended for direct connection to driver circuits which deliver symmetrical current signals, but is also suitable for asymmetrical currents. The current to voltage conversion is done by the external resistor (Rcon) connected between the output of the input conversion stage and output stage B. This voltage is compared with the output current through the deflection coil measured as voltage across RM, which provides internal feedback information. The relationship between the differential input current and the output current is defined by: 2 x Ii(diff) x Rcon = Icoil x RM The output current is adjustable from 0.5 A (p-p) to 3.2 A (p-p) by varying Rcon. The maximum input current is 800 A peak for each pin. The minimum input current should be 50 A. Flyback supply The flyback voltage is determined by an additional supply voltage Vflb. The principle of operating with two supply voltages (class G) makes it possible to fix the supply voltage VP optimum for the scan voltage and the second supply voltage Vflb optimum for the flyback voltage. Using this method, very high efficiency is achieved. The supply voltage Vflb is almost totally available as flyback voltage across the coil, this being possible due to the absence of a coupling capacitor (not necessary, due to the bridge configuration). The very short rise and fall time of the flyback switch is >400 V/s.
handbook, halfpage
Vo(guard) Vi(M) Vi(con) VP(B) Vo(B) GNDB Vflb GNDA Vo(A)
1 2 3 4 5 6
TDA8354Q
7 8 9
Protection The output circuit has protection circuits for: * Die temperature control * Overvoltage of output stage A.
VP(A) 10 Ii(neg) 11 Ii(pos) 12 Ii(comp) 13
MGL462
The die has been glued to the metal block of the package. If the metal block is not insulated from the heat sink, the heat sink may only be connected directly to pins 6 and 8.
Fig.2 Pin configuration.
1998 Sep 03
4
Philips Semiconductors
Preliminary specification
Full bridge current driven vertical deflection output circuit in LVDMOS
Guard circuit A guard circuit with output signal Vo(guard) is provided. The guard circuit generates an active HIGH level during the flyback period. The guard circuit is also activated for one or more of the following conditions: * When the thermal protection is activated (Tj 170 C) * During short-circuit of the output pins (pins 5 and 9) to VP or ground * During open coil * During open loop * During short-circuit of the input pins (pins 11 and 12) to VP or ground. An active HIGH level of the guard signal is also generated for the next conditions: * No drive signal * Short-circuit of the coil. However, for these events the signal is generated via an internal timer circuit. The guard signal set via this timer has a delay of 120 ms. The delay time is given by the lowest applicable field frequency. The guard signal can be used for blanking the picture tube screen and signalling a fault condition. Damping resistor compensation
TDA8354Q
For HF-loop stability a damping resistor is connected across the deflection coil. There is a big difference in current in the damping resistor Rp during scan and flyback. The resistor current is summed to the current in the deflection coil via the measuring resistor RM, which results in a too low current in the deflection coil at the start of the scan. To reach a short settling time the difference in the current during scan and flyback in the damping resistor can be compensated for by external means. To do so a resistor (Rcomp) of about 1 M can be connected between the output of stage A (pin 9) and the damping resistor compensation current input (pin 13). For a more accurate calculation of Rcomp refer to the following formula: ( V flb - V loss - V P ) x R p x R con R comp = -------------------------------------------------------------------------------( V flb - V loss - I L x R L ) x R M
1998 Sep 03
5
Philips Semiconductors
Preliminary specification
Full bridge current driven vertical deflection output circuit in LVDMOS
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL DC supply VP Vflb Io(p-p) Vo(A) Vo(B) I1,2,3,11,12,13 V1,2,3,11,12,13 Io(Vflb) Tstg Tamb Tj tsc Ii/o VESD supply voltage flyback supply voltage - - - note 1 - - -20 -0.5 - -55 -25 note 2 - - - -200 - - PARAMETER CONDITIONS MIN.
TDA8354Q
MAX.
UNIT
18 68
V V
Vertical circuit output current (peak-to-peak value) output voltage (pin 9) output voltage (pin 5) current into or out of pins 1 to 3 and 11 to 13 peak voltage on pins 1 to 3 and 11 to 13 3.2 68 VP +20 VP 1.6 A V V mA V
Flyback switch peak output current A C C C
Thermal data (in accordance with IEC 747-1) storage temperature operating ambient temperature junction temperature +150 +75 150
Miscellaneous short-circuiting time current into any pin current out of any pin electrostatic handling note 3 +1.5 x VP(max); note 4 -1.5 x VP(max); note 4 note 5 note 6 Notes 1. When the pin voltage exceeds 70 V the device behaves like a power zener diode thus limiting the voltage. 2. Internally limited by thermal protection; switching point 170 C. 3. Up to VP = 18 V. 4. At Tj(max). 5. Machine model: equivalent to discharge a 200 pF capacitor through a 0 series resistor. Except pin 7: 250 V. 6. Human body model: equivalent to discharge a 100 pF capacitor through a 1.5 k series resistor. Except pin 7: 1500 V. 1 +200 - 300 2000 h mA mA V V
1998 Sep 03
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Philips Semiconductors
Preliminary specification
Full bridge current driven vertical deflection output circuit in LVDMOS
THERMAL CHARACTERISTICS SYMBOL Rth(j-c) Rth(j-a) PARAMETER thermal resistance from junction to case thermal resistance from junction to ambient in free air CONDITIONS
TDA8354Q
VALUE 4 40
UNIT K/W K/W
CHARACTERISTICS VP = 12 V; Vflb = 45 V; fi = 50 Hz; Ii(bias) = 330 A; Tamb = 25 C; measured in test circuit of Fig.3; unless otherwise specified. SYMBOL DC supply VP Vflb Iq(av) Iq IVflb(av) Vloss operating supply voltage flyback supply voltage average quiescent supply current quiescent supply current average flyback supply current during scan no signal; no load during scan 7.5 2 x VP - - - - - Io = 2.2 A (p-p); note 1 - - 12 45 10 60 - - - - - 18 68 15 80 10 V V mA mA mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Output stage A and B voltage loss from pin 10 to 9 and from pin 5 to 6 voltage loss from pin 4 to 5 and from pin 9 to 8 voltage loss from pin 10 to 9 and from pin 5 to 6 voltage loss from pin 4 to 5 and from pin 9 to 8 LE linearity error adjacent blocks not adjacent blocks Vo Voffset output voltage swing (flyback) Vo(A) - Vo(B) offset voltage across RM Io = 3.2 A (p-p); note 2 Io = 3.2 A (p-p); note 2 Ii(diff) = 0.3 mA; Io = 1.6 A Ii(diff) = 0 Ii(bias) = 500 A Ii(bias) = 100 A Voffset(T) Vo(A), Vo(B) Gv(ol) fres Gi offset voltage as function of temperature DC output voltage Ii(diff) = 0 Ii(diff) = 0; note 3 notes 4 and 5 note 4 open loop - - - - - - - - - - - VP -----2 60 0 1 8000 15 13 40 - - - - - mV mV V/K V - - - 0.5 0.5 46 2 3 - % % V Io = 3.2 A (p-p); note 1 6.0 4.8 4.2 3.4 V V V V
open-loop voltage gain V9 to 5/V3 to 5 frequency response (-3 dB) current gain (Io/Ii(diff))
dB dB kHz
V3 to 5/V2 to 5 voltage ratio V3 to 5/V2 to 5
1998 Sep 03
7
Philips Semiconductors
Preliminary specification
Full bridge current driven vertical deflection output circuit in LVDMOS
SYMBOL Gi(T) PSRR Input stage Ii(bias) Ii(diff)(p-p) Vi(diff) Vi(cm) Io(Vflb) Vloss Io(guard) signal bias current differential mode input current (peak-to-peak value) pin 11 or 12 differential mode input voltage common mode input voltage note 7 Ii(diff) = 500 A Ii(bias) = 330 A t < 1.5 ms Io = +1.6 A not active; Vo(guard) = 0 V Io(guard) = 100 A maximum leakage current = 10 A - - - 0.95 - - - 330 500 0.75 1.15 - 8 - - 6 - PARAMETER current gain drift as function of temperature power supply rejection ratio note 6 CONDITIONS - 80 MIN. - 90 TYP.
TDA8354Q
MAX. 10-4 -
UNIT /K dB A A V V
500 600 - 1.35 1.6 9
Flyback switch output peak current voltage loss (Vflb - Vo(A)) output current A V A mA V V
Guard circuit 10 2.5 7 18
active; Vo(guard) = 4.5 V 1 Vo(guard) output voltage on pin 1 allowable voltage on pin 1 Notes 1. At Tj = 125 C. The temperature coefficient of Vloss has a positive sign. 5 -
2. The linearity error is measured without S correction and based on the same measurement principle as performed on the screen. The measuring method is as follows: Divide the output signal into 22 equal time parts ranging from 1 to 22 inclusive. Measure the value of the voltage across RM of two succeeding parts called one block (a) starting with part 2 and 3 (block 1) and ending with part 20 and 21 (block 10). Thus parts 1 and 22 are unused. The equations for linearity error for adjacent blocks (LEAB) and not adjacent blocks (LENAB) are given below: ak - a ( k + 1) LEAB = ----------------------------a av a max - a min LENAB = ----------------------------a av 3. Vo(A) + Vo(B) = VP. At the start of the scan this equation is one diode voltage less. 4. The V value within formulae relates to voltages at or between relative pin numbers, i.e. V9 to 5/V3 to 5 = voltage value across pins 9 and 5 divided by voltage value across pins 3 and 5. 5. V2 to 5 AC short-circuited. 6. At V(ripple) = 500 mV (eff) at VP; measured across RM; f(ripple) = 50 Hz - 1 kHz. 7. Ii(bias) + Ii(diff) 800 A and Ii(bias) - Ii(diff) 50 A per pin.
1998 Sep 03
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Philips Semiconductors
Preliminary specification
Full bridge current driven vertical deflection output circuit in LVDMOS
INTERNAL CIRCUITRY Table 1 PIN 1 Equivalent pin circuits SYMBOL Vo(guard)
1 300
TDA8354Q
EQUIVALENT CIRCUIT
MGL472
2
Vi(M)
2
300
MGL465
3
Vi(con)
300
3
MGL466
4 5 6
VP(B) Vo(B) GNDB
4
5
6
MGL467
1998 Sep 03
9
Philips Semiconductors
Preliminary specification
Full bridge current driven vertical deflection output circuit in LVDMOS
PIN 7 8 9 10 Vflb GNDA Vo(A) VP(A)
9
TDA8354Q
SYMBOL
EQUIVALENT CIRCUIT
10
8 7
MGL471
11
Ii(neg)
300
11
MGL470
12
Ii(pos)
300
12
MGL469
13
Ii(comp)
300
13
MGL468
1998 Sep 03
10
Philips Semiconductors
Preliminary specification
Full bridge current driven vertical deflection output circuit in LVDMOS
TEST AND APPLICATION INFORMATION
TDA8354Q
handbook, full pagewidth
VP R(guard) Vo(guard) 1 GUARD CIRCUIT VP(B) 4 VP(A) 10 Vflb 7 C3 C4 Vflb
Ii(diff) Ii(bias) Ii(diff) Ii(bias) Ii(pos) 12
9
Vo(A) Rcomp Rp
RL
coil
Ii(diff) Ii(diff) INPUT/ FEEDBACK
COMPENSATION 13 Ii(comp) CIRCUIT V 2 i(M)
Rs RM
3 11 Ii(neg) Ii(bias) Ii(diff) Ii(bias) Ii(diff)
Vi(con)
Rcon
5 Vo(B)
TDA8354Q
6 GNDB 8 GNDA
MGL463
Fig.3 Test diagram.
1998 Sep 03
11
Philips Semiconductors
Preliminary specification
Full bridge current driven vertical deflection output circuit in LVDMOS
TDA8354Q
handbook, full pagewidth
VP R(guard) Vo(guard) 1 GUARD CIRCUIT VP(B) 4 VP(A) 10 Vflb 7 C3 C1 C4 C5 C2 Vflb
Ii(diff) Ii(bias) Ii(diff) Ii(pos) C6 COMPENSATION 13 Ii(comp) CIRCUIT V 2 i(M) 12 9 Vo(A) Rcomp Rp coil
DEFLECTION PROCESSOR
INPUT/ FEEDBACK
Rs RM
Ii(neg) C7
3 11
Vi(con)
Rcon
5 Vo(B)
Ii(diff) Ii(bias) Ii(diff)
TDA8354Q
6 GNDB 8 GNDA
MGL464
Coil: AT6216/42; VP = 12.1 V at fv = 50 Hz (vertical frame frequency); inclusive spread (absolute) and temperature rise in the coil; VP = 12.8 V at fv = 100 Hz (vertical frame frequency); inclusive spread (absolute) and temperature rise in the coil; Io(p-p) = 2.33 A (peak-to-peak); Ii(bias) = 330 A; Ii(diff)(12-11) = 485 A (peak value); Vflb = 45 V; tflb = 0.6 ms.
RM = 0.5 ; Rcon = Rs = 1.2 k; Rp = 300 ; Rcomp = 650 k; R(guard) = 5 k.
C1 = 47 F; 100 V; C2 = 220 F; 25 V; C3 = C4 = 100 nF; C5 = 10 nF; C6 = C7 = 10 nF.
Fig.4 Application diagram.
1998 Sep 03
12
Philips Semiconductors
Preliminary specification
Full bridge current driven vertical deflection output circuit in LVDMOS
PACKAGE OUTLINE DBS13P: plastic DIL-bent-SIL power package; 13 leads (lead length 12 mm)
TDA8354Q
SOT141-6
non-concave x D Dh
Eh
view B: mounting base side
d
A2
B j E A
L3
L
Q c vM
1 Z e e1 bp wM
13 m e2
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A 17.0 15.5 A2 4.6 4.2 bp 0.75 0.60 c 0.48 0.38 D (1) 24.0 23.6 d 20.0 19.6 Dh 10 E (1) 12.2 11.8 e 3.4 e1 1.7 e2 5.08 Eh 6 j 3.4 3.1 L 12.4 11.0 L3 2.4 1.6 m 4.3 Q 2.1 1.8 v 0.8 w 0.25 x 0.03 Z (1) 2.00 1.45
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT141-6 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-03-11 97-12-16
1998 Sep 03
13
Philips Semiconductors
Preliminary specification
Full bridge current driven vertical deflection output circuit in LVDMOS
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (order code 9398 652 90011). Soldering by dipping or by wave The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA8354Q
The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Repairing soldered joints Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds.
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1998 Sep 03
14
Philips Semiconductors
Preliminary specification
Full bridge current driven vertical deflection output circuit in LVDMOS
NOTES
TDA8354Q
1998 Sep 03
15
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545104/00/01/pp16
Date of release: 1998 Sep 03
Document order number:
9397 750 04083

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